留学生电子工程代考 ELEC0009 – LSA Simulation Laboratory

ELEC0009 – LSA Simulation Laboratory 2021

留学生电子工程代考 onfigure the circuit in (3) above as a unity gain buffer. Simulate the circuit to obtain the -3 dB frequency. Then, apply a step

You are expected to complete the following set of simulation tasks using Multisim. Your submission is an electronic lab-book as a .PDF file.
Please note that you are NOT expected to write a report, but your submission is an electronic labbook populated by results, calculations, and very brief notes. This is an individual assignment, and you should work on your own to complete the tasks.

Task A:  留学生电子工程代考

This task is primarily on large signal analysis. While here we refer to total signal values (e.g. iC) for completeness, in each case you should consider a DC/large signal change. Then from this large
signal analysis you should derive small signal parameters.
1. From the available Multisim library of transistors, select one BJT and one enhancement MOSFET. If you select an npn BJT you must select a PMOS transistor, and if you select a pnp
BJT you must select an NMOS transistor. Indicating their key features, very briefly comment on your selections.
2. Plot iC vs. vCE for different vBE values on the same graph and estimate ro for the selected BJT based on the plots. 留学生电子工程代考

1. Evaluate β for the BJT using a simulation setup.


2. Plot iC vs. vBE and estimate gm and rπ for a given VBE for the selected BJT.


3. Plot iD vs. vDS for different vGS values on the same graph and estimate ro for the selected MOSFET based on the plots.


4. Plot iD vs. vGS and estimate gm for a given VGS for the selected MOSFET.

Task B:

In this task, you must use the transistors you have selected in Task A and observe the following:
• You MUST at least once design a BJT circuit and you MUST at least once design a MOSFET circuit.
• You should use an ideal sinusoidal input voltage signal with an amplitude of 40 mV (vsig). vsig must have a resistor in series with it (Rsig). In two of the following subtasks you should use Rsig = 100 kΩ and only in one of the subtasks you should use Rsig = 100 Ω. You should justify your choices briefly.

• You only have access to two DC supply voltages set at any value between - 6 V to + 6 V.
• You should consider a load resistance RL = 60 kΩ.
• You have access to any number of resistors and capacitors of any value. You should appropriately bias the transistors in the circuits and AC-couple input and output voltage
signals.  留学生电子工程代考

• You should use source or emitter degeneration resistors in all three circuits.
• Your key priority is to maximise gain in each circuit. You should clearly demonstrate how you achieve this goal.
• Your other design decision is to ensure that lower -3dB corner frequency is no more than 60 Hz. If you cannot achieve this goal explain why.
• In each case clearly demonstrate your designs and, include calculations, brief notes on design choices you make and include appropriate simulation results and graphs to indicate successful implementation of your design. Evaluate the designs at low frequencies, midband and high frequencies.

1. Design and simulate either a common emitter or a common source amplifier circuit.


2. Design and simulate either a common base or a common gate amplifier circuit.


3. Design and simulate either a common collector or a common drain amplifier circuit.

Task C:  留学生电子工程代考

Using the parameters and models of the NPN bipolar transistor 2N2102 and the PNP bipolar transistor 2N2905 available in Multisim:
1. Simulate a NPN simple current mirror to obtain its small-signal output resistance and the current copying accuracy for an input current of 0.5 mA. Compare your results with hand
calculations. Assume a supply voltage of +/- 5 V.
2. Simulate a PNP Wilson current mirror to obtain its small-signal output resistance and the current copying accuracy for an input current of 0.5 mA. Compare your results with hand
calculations. Assume a supply voltage of +/-5 V.

1. Construct a differential amplifier with active PNP load and the tail current provided by the current mirror in (1) above. Assume a supply voltage of +/- 10 V. For a bias current of 1 mA
   (to the input of the current mirror), simulate the circuit to obtain the small-signal differential and common-mode gains and the -3 dB frequency.


2. Replace the active load in (3) above with two resistive loads of value 1 kΩ each. Simulate the large-signal dc transfer characteristics of the collector currents of the differential pair transistors and establish the input linear range of operation. Modify your circuit to increase the input linear range by a factor of 3.  留学生电子工程代考




3. Configure the circuit in (3) above as a unity gain buffer. Simulate the circuit to obtain the -3 dB frequency. Then, apply a step input of 5 V peak-to-peak and report the slew rate.



4. Modify the circuit in (5) above to perform as a low-pass filter with a cut-off frequency of 10 kHz. What is the roll-off of your filter?

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